Design Verification Intern, MS - Summer 2027
marvell · Santa Clara, CA · United States · On-site
Posted Sep 4, 2026
Sign up free: we match you to jobs like this, tailor your application and fill the form. 2 free applications every day.
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell’s Design Verification teams span across multiple domains, giving you the opportunity to work on technologies that power next-generation cloud, AI, storage, and networking solutions. Some teams focus on pre-silicon emulation and verification for ODSP-related chips. Other teams focus on ASIC Design, where they testbench with UVM methodology and test specific SOC designs at block/cluster/full chip levels. Other teams focus on powering the full range of network connectivity from the optics of the AI GPU boards to top of the rack optical fibers and active copper cables of the data centers and their fabrics. Across all groups, you’ll collaborate with your direct team and cross-functional partners (across software, physical design, digital design, and more) to deliver robust, scalable solutions that enable Marvell’s leadership in data infrastructure.
What You Can Expect
Dive deep into the architecture of our cutting-edge processors and learn exactly how they function
Use industry-standard tools to create powerful simulation environments that mimic real-world conditions
Develop smart, automated tests that push our designs to their limits , creatively trying to "break" the chip to find & troubleshoot hidden flaws & failed simulations
Analyze test coverage results & metrics
Collaborate with chip architects and designers to solve complex problems and contribute to a team building real products
What We're Looking For
Currently enrolled in a Master' s Degree in Ele ctrical Engineeri ng , Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028
Completed courses focusing on computer architecture, logic, processor, memory system, V erilog , VLSI, VHDL, UVM, analog, integrated circuit design, digital logic design, SoC/ASIC design, verification principles, signals, system and signal processing
Proficiency in programming & scripting languages like Python, C, C++, Perl, Java
Experience using tool s like Synopsys, Cadence, or Mentor to run simulations and write & debug a testbench
Hands-on experience with RTL integration and bring-up system
Experience with debugging complex hardware/software interactions
Strong analysis, problem solving, and communication skills
Expected Base Pay Range (USD)
35 - 70, $ per…