Senior CPU Design Verification Engineer

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.   Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.  Are you ready?   To learn more about SiFive’s phenomenal success and to see why we have won the   GSA’s prestigious Most Respected Private Company Award   (for the fourth time!), check out our   website   and   Glassdoor   pages. Job Description:   Role Summary We are seeking a Senior CPU Design Verification Engineer to own block‑ and subsystem‑level DV for advanced out‑of‑order (OoO) CPU cores . You will work closely with micro‑architects and RTL designers to verify complex Front end Designs includes branch prediction, Instruction decodes, execution pipelines, memory systems, and coherence protocols using modern, coverage‑driven methodologies. Key Responsibilities Verification Planning & Ownership Drive verification for key OoO CPU blocks, such as: Front‑end: fetch, branch prediction, decode. Rename and register mapping. Issue queues / schedulers and execution units. Reorder buffer (ROB), retirement, exceptions, and flush/replay. Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences. L1 caches, TLBs, MMU interfaces, and coherence interfaces. Derive verification plans from architecture and micro‑architecture specs, with emphasis on: Speculative execution flows and pipeline hazards. Memory ordering / consistency model compliance. Interaction with cache hierarchy and coherence. Testbench & Environment Development Develop and maintain  SystemVerilog/UVM  testbenches: UVM agents, monitors, scoreboards, reference models. Constrained‑random stimulus and directed tests for OoO corner cases. Implement self‑checking mechanisms for: Instruction retirement and architectural state. LSU / memory ordering, atomics, and fence behavior. TLB, page‑table, and privilege/protection flows as needed. Coverage & Quality Define and track  functional, code, and assertion coverage ; identify gaps and add tests/monitors to…