Senior/Staff Front-End Engineer (RISC Processor Integration)

About Bitdeer: Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud. Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence. Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia. Job Summary: We are seeking an experienced SoC Design Engineer to develop next-generation System-on-Chip (SoC) solutions. The ideal candidate will have hands-on experience implementing RISC processors (e.g., RISC-V or Arm), including processor configuration, subsystem integration, memory architecture, interconnects, and system bring-up. This role involves working closely with architecture, RTL, verification, software, and physical design teams throughout the SoC development lifecycle. What you will be responsible for: Configure and integrate RISC processor IP (RISC-V or Arm) into SoC platforms. Customize processor features, including cache configuration, MMU/MPU, PMP, debug, interrupt controller, and privilege modes. Integrate processor subsystems with: AXI/AHB/APB interconnects Interrupt controller (PLIC/GIC/NVIC) Develop RTL integration logic, wrappers, and system glue logic. Collaborate with verification teams to develop test plans and debug simulation issues. Work with firmware and software teams to enable bootloader, BSP, and operating system bring-up. Analyze and resolve system-level performance, power, and integration issues. Review third-party IP documentation and coordinate IP integration. How you will stand out: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience in SoC design, processor integration, or related semiconductor development. Strong experience integrating RISC processors, particularly RISC-V, into complex SoC platforms. Solid understanding of processor architecture, including: Pipeline architecture Cache hierarchy MMU/MPU/PMP Interrupt and exception handling Debug architecture Experience with AMBA bus protocols (AXI4, AHB, APB). Strong RTL design skills using Verilog/SystemVerilog. Experience with RTL development flows, including synthesis, lint, CDC analysis, and RTL quality checks. Familiarity with SoC boot flow and firmware interaction. Experience with simulation and debugging tools such as VCS, Xcelium, Questa, Verdi, or equivalent. Good understanding of clock/reset architecture and low-power design…