Staff Engineer, Physical Design - High Speed Interconnects

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits. At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.   Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.  Are you ready?   To learn more about SiFive’s phenomenal success and to see why we have won the   GSA’s prestigious Most Respected Private Company Award   (for the fourth time!), check out our   website   and   Glassdoor   pages. Job Description:   About the Role - As a Staff Physical Design Engineer (High-Speed Interconnects), you will be responsible for the end-to-end implementation of high-bandwidth Network-on-Chip (NoC) and Uncore subsystems.  This is not a traditional "siloed" backend role; you will operate at the intersection of architecture, design and physical implementation. You will drive PPA (Power, Performance, Area) outcomes by influencing RTL structures and floorplanning strategies early in the design cycle. Your expertise in advanced process nodes and system-level data flow will be critical in delivering scalable, high-frequency IP that forms the backbone of our next-generation compute platforms. Responsibilities - What You’ll Do End-to-End Implementation: Execute the full physical design flow (RTL-to-GDSII) for complex NoC and Uncore subsystems, ensuring timing closure and routability for interconnects. Architecture & PD Co-Design: Partner with RTL and Architecture teams to perform early-stage feasibility analysis. Identify physical bottlenecks in the microarchitecture and propose RTL restructuring, such as optimized pipelining or bus-width adjustments, to meet PPA targets. Advanced Floorplanning: Own hierarchical partitioning and macro placement. You will define the physical blueprint for massive die areas, optimizing pin assignments and global routing tracks to minimize latency across the fabric. Interconnect Problem Solving: Solve unique NoC challenges, including long-wire RC compensation, repeater strategy for global signals, and complex clock/reset distribution across hierarchies. Methodology Innovation: Develop…